1. Field of the Invention
The present invention relates to a semiconductor device for outputting a constant reference voltage.
2. Description of the Related Art
Up to now, a circuit shown in FIG. 2 is used as a reference voltage circuit in which a stable output voltage is obtained regardless of variations in power source voltage and temperature (for example, see JP 04-065546 B (pp.6 and 7, FIG. 2)).
With respect to a configuration of the circuit, the source of a depletion mode (or type) MOS transistor 1 and the drain of an enhancement mode (or type) MOS transistor 2 having the same conductivity type are connected in series with each other. The gate and the source of the depletion type MOS transistor 1 are connected with each other. The gate and the drain of the enhancement type MOS transistor 2 are connected with each other. A high voltage supply terminal 100 is provided at the drain of the depletion type MOS transistor 1. A low voltage supply terminal 101 is provided at the source of the enhancement type 1405 transistor. An output terminal 110 is provided at a connection point of both the above-mentioned MOS transistors. Hereinafter, such a circuit is called an ED type (enhancement depletion type) reference voltage circuit. The terminal 100 is assumed to be a high voltage supply terminal of an ED type reference voltage.
The reference voltage circuit should ideally output a constant voltage even in the case of any voltage. However, actually, an output voltage is varied according to an applied voltage. Thus, there is the case where a cascode circuit for keeping a voltage applied to the ED type reference voltage circuit constant is added.
FIG. 3 shows an example of an ED type reference voltage circuit added with a cascode circuit for keeping a voltage applied to the ED type reference voltage circuit constant between the high voltage supply terminal 112 of the ED type reference voltage circuit and a high voltage supply terminal 100.
The high voltage supply terminal 112 of the ED type reference voltage circuit (the drain of the depletion type MOS transistor 1) and the source of a MOS transistor 7 having the same conductivity type are connected in series with each other. The drain of the MOS transistor 7 having the same conductivity type is connected with the high voltage supply terminal 100. Thus, it is constructed that a constant voltage is supplied from a constant voltage source 10 to the gate. According to such a configuration, when a voltage at the high voltage supply terminal 100 is a certain voltage or higher, the voltage applied to the high voltage supply terminal 112 of the ED type reference voltage circuit becomes a constant voltage. Thus, even when the voltage at the high voltage supply terminal 100 is varied, there is no case where a voltage at the output terminal 110 of the ED type reference voltage circuit is influenced by the variation.
FIG. 4 shows a circuit in the case where two ED type reference voltage circuits each having the above configuration are used. In the case of the circuit shown in FIG. 4, the same voltage is supplied to transistors 7 and 8 having the same conductivity type for which cascode connection is made. However, a voltage between the gate and the source is changed for the respective transistors 7 and 8 having the same conductivity type due to a cause such as mask shift. Thus, a voltage difference is produced between high voltage supply terminals 112 and 113 of the respective ED type reference voltage circuits so that there is the case where a difference of output voltages is caused due to a difference of voltages applied to the high voltage supply terminals of the ED type reference voltage circuits. Accordingly, this becomes a problem in the case where it is required that voltages at output terminals 110 and 111 of two reference voltage circuits are matched with high precision.
According to the present invention, in order to solve the above-mentioned problem, the source of a depletion type MOS transistor is connected in series with the drain of a depletion type MOS transistor in each of two ED type reference voltage circuits, the gate of one of the series-connected depletion type MOS transistors is connected with the source of the other MOS transistor and the gate of the other MOS transistor is connected with the source of the one MOS transistor. Thus, a difference of voltages applied to the respective ED type reference voltage circuits is reduced.
A reference voltage circuit according to the present invention includes: a first voltage terminal; a second voltage terminal; a first ED type reference voltage circuit connected between the first voltage terminal and the second voltage terminal; and a first depletion MOS transistor connected between the first voltage terminal and the first ED type reference voltage circuit. The reference voltage circuit further includes: a second ED type reference voltage circuit connected between the first voltage terminal and the second voltage terminal; and a second depletion MOS transistor connected between the first voltage terminal and the second ED type reference voltage circuit. Further, in the reference voltage circuit, a gate terminal of the first depletion MOS transistor is connected with a potential between the second ED type reference voltage circuit and the second depletion MOS transistor, and a gate terminal of the second depletion MOS transistor is connected with a potential between the first ED type reference voltage circuit and the first depletion MOS transistor.
Further, the reference voltage circuit according to the present invention is characterized in that: the first and second ED type reference voltage circuits each includes a depletion MOS transistor and an enhancement MOS transistor which are connected in series with each other; and a gate electrode of the depletion MOS transistor and a gate electrode of the enhancement MOS transistor are common and a voltage on a connection point of the depletion MOS transistor and the enhancement MOS-transistor is used as an output.
An electronic device according to the present invention is characterized by including the above-mentioned reference voltage circuit.